ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

PLL Dynamic Reconfiguration

The PLL Dynamic Reconfiguration feature allows you to reconfigure your PLL on-the-fly. You can control the configuration process using the following ports:

  • Input ports: scanclk, scandata, scanclkena, and configupdate.
  • Output ports: scandataout and scandone. The scandone port is not available for Cyclone, Cyclone II, Stratix, and Stratix GX devices.

The Stratix and Stratix GX enhanced PLLs can be dynamically reconfigured using scan chains. Depending on the PLL type, two options are available for the scan chain – long or short. The long scan chain allows the configuration of those PLLs with six core and four external clocks, while the short scan chain limits the configuration to those PLLs with the six core clocks with no external clocks.

The scan chain method for dynamic reconfiguration is not available for all supported device families. The devices that support the normal dynamic reconfiguration scheme uses configuration files, such as the Hexadecimal-format file, .hex, or the Memory Initialization file, .mif. These files are used together with the ALTPLL_RECONFIG IP core to perform the dynamic configuration.

In the ALTPLL IP core, you should not use self-reset on loss of lock when implementing the PLL reconfiguration. The PLL may lose lock when PLL reconfiguration completes. If self-reset on loss of lock is enabled, the SCANDONE signal is cleared. This may violate the minimum pulse width required to sample SCANDONE asserted at the ALTPLL_RECONFIG IP core.

If the ALTPLL_RECONFIG IP core does not detect SCANDONE asserted, the busy signal remains high. No further reconfiguration operations are possible until the ALTPLL_RECONFIG IP core is reset by user logic. The ALTPLL_RECONFIG IP core automatically resets the PLL when reconfiguration is complete.