ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Operation Modes

The ALTPLL IP core supports up to five different clock feedback modes, depending on the selected device family. Each mode allows clock multiplication and division, phase shifting, and duty-cycle programming.

The following list describes the operation modes for the ALTPLL IP core:

  • Normal mode—The PLL feedback path source is a global or regional clock network, minimizing clock delay to registers for that clock type and specific PLL output. You can specify PLL output that is compensated in normal mode.
  • Source-Synchronous mode—The data and clock signals arrive at the same time at the data and clock input pins. In this mode, the signals are guaranteed to have the same phase relationship at the clock and data ports of any Input Output Enable register.
  • Zero-Delay Buffer mode—The PLL feedback path is confined to the dedicated PLL external clock output pin. The clock port driven off-chip is phase aligned with the clock input for a minimal delay between the clock input and the external clock output.
  • No Compensation mode—The PLL feedback path is confined to the PLL loop. It has no clock network or other external source. A PLL in no-compensation mode has no clock network compensation, but clock jitter is minimized.
  • External Feedback mode—The PLL compensates for the fbin feedback input to the PLL. The delay between the input clock pin and the feedback clock pin is minimized.