ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Parameter Settings

For devices that support the advanced control signals—pllena, pfdena, and areset, the parameter settings for these signals are located on the Inputs/Lock or Scan/Inputs/Lock page of the ALTPLL parameter editor.

The following figure shows the options related to the advanced control signals. Turn on the control signal you want to create from the options available.

Figure 8. Options to Select the Advanced Control Signals

The deassertion of the pllena signal or the assertion of the areset signal does not disable the VCO, but instead resets the VCO to its nominal value. The only time that the VCO is completely disabled is when you do not have a PLL instantiated in your design.