ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Implementing the ddr_clk Design

To assign the EP1S10F780 device to the project and compile the project, follow these steps:

  1. On the Assignments menu, click Settings. The Settings dialog box appears.
  2. In the Category list, click Device. Select Stratix in the Device Family field.
  3. In the Target device section, under Available devices, select EP1S10F780C5.
  4. Click OK.
  5. On the Processing menu, click Start Compilation.
  6. When the Full Compilation was successful message box appears, click OK.
  7. To view how the module is implemented in the Stratix device, on the Assignments menu, click Timing Closure Floorplan.
The ddr_clk design is now implemented.