ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Public
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ALTPLL Bidirectional Port

Table 17.  ALTPLL Bidirectional Output Port

Port Name

Condition

Description

fbmimicbidir

Optional

The bidirectional port that connects to the mimic circuitry. This port is available only for Stratix III and Stratix IV device families, and only when the PLL is in zero-delay buffer mode. This port must be connected to a bidirectional pin that is placed on the positive feedback dedicated output pin of the PLL.