ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Generating a 166-MHz Differential SSTL External Clock

To generate a 166-MHz Differential SSTL external clock, follow these steps:

Download and unzip the .

  1. In the Quartus® Prime software, open the project file \ddr_clk\ddr_clk.qpf.
  2. Open the top-level \ddr_clk\ddr_clk.bdf file. You will complete this project in this example.
  3. Click Tools > IP Catalog. Then expand the I/O folder and select ALTPLL
  4. In Which type of output file do you want to create?, select AHDL.
  5. For What name do you want for the output file?, name the output file ddr_pll.
  6. For What is the frequency of the inclock0 input?, type 33.33, and select MHz.
  7. Under PLL type, click Select the PLL type automatically.
  8. Under Operation mode, select Create an 'fbin' input for an external feedback (External Feedback Mode).
  9. Under Operation mode, for Which output clock will have a board level connection?, select e0 from the drop‑down menu.
  10. In the Dynamic configuration section, turn off Create optional inputs for dynamic reconfiguration.
  11. In the Optional inputs sections:
    1. Turn on Create an ‘pllena’ input to selectively enable the PLL.
    2. Turn on Create an ‘areset’ input to asynchronously reset the PLL.
    3. Turn off Create an ‘pfdena’ input to selectively enable the phase/frequency detector.
  12. In the Lock output section, turn on Create ‘locked’ output.
  13. Leave the remaining options at their default settings.
  14. Click the Output Clocks tab.
  15. Click extclk e0.
  16. Turn on Use this clock.
  17. Turn on Enter output clock parameters, and in the Clock multiplication factor box, type 5.
  18. In the Clock division factor box, type 1.
  19. In the Clock duty cycle (%) box, type 50.00.
  20. Click Next.
  21. On page 14, repeat step 16 through step 19 for extclk e1.
  22. Click Next.
  23. On page 15, repeat step 16 through step 19 for extclk e2.
  24. Click Next.
  25. On page 16, repeat step 16 through step 19 for extclk e3.
  26. Click Next. Page 17 appears. No input is required for this page.
  27. Click Next. Page 18 appears.
  28. On page 18, ensure that the Text Design File (.tdf), Pin Planner File (.ppf), AHDL Include File (.inc), Block Symbol File (.bsf), and Sample waveforms in summary file (.html and .jpg) are turned on.
  29. Click Finish. The ddr_pll module is built.
  30. In the Symbol dialog box of the .bdf file, click OK.
  31. Move the pointer to place the ddr_pll symbol between the input and output ports in the ddr_clk.bdf file, connecting the inputs and outputs to the symbol. Click to place the symbol.
  32. Save the design.
The following figure shows a completed design file.
Figure 21. ALTPLL ddr_pll Design Schematic