ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Design Examples

The design examples use the ALTPLL IP core to:

  • Generate an external differential clock from an enhanced PLL.
  • Generate and modify internal clock signals.

These examples use the IP Catlog and parameter editor. When you complete the examples, you can incorporate them into your projects.

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