ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software

This ModelSim design example is for the ModelSim‑Altera (Verilog) version. To simulate the design in the ModelSim-Altera software, follow these steps:

  1. Unzip file to any working directory on your PC.
  2. Locate the folder in which you unzipped the files to and open the file in a text editor.
  3. In line 1, replace <insert_directory_path_here> with the directory path of the appropriate library files. For example, C:/Modeltech_ae/altera/verilog/stratix
  4. On the File menu, click Save.
  5. Start the ModelSim-Altera software.
  6. On the File menu, click Change Directory.
  7. Select the folder in which you unzipped the files. Click OK.
  8. On the Tools menu, click TCL, and click Execute Macro.
  9. Select the file and click Open. The file is a script file for the ModelSim-Altera software to automate all the necessary settings for the simulation.
  10. Verify the results shown in the Waveform Viewer window.
The following figure shows the expected simulation results in the ModelSim-Altera software.
Figure 22. ModelSim Simulation Results