Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
This ModelSim design example is for the ModelSim‑Altera (Verilog) version. To simulate the design in the ModelSim-Altera software, follow these steps:
- Unzip ddr-clk-msim.zip file to any working directory on your PC.
- Locate the folder in which you unzipped the files to and open the DDR_CLK.do file in a text editor.
- In line 1, replace <insert_directory_path_here> with the directory path of the appropriate library files. For example, C:/Modeltech_ae/altera/verilog/stratix
- On the File menu, click Save.
- Start the ModelSim-Altera software.
- On the File menu, click Change Directory.
- Select the folder in which you unzipped the files. Click OK.
- On the Tools menu, click TCL, and click Execute Macro.
- Select the DDR_CLK.do file and click Open. The DDR_CLK.do file is a script file for the ModelSim-Altera software to automate all the necessary settings for the simulation.
- Verify the results shown in the Waveform Viewer window.
The following figure shows the expected simulation results in the ModelSim-Altera software.
Figure 22. ModelSim Simulation Results
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