ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing

The ALTLVDS IP core provides SERDES transmitter and receiver functionality commonly used in LVDS interfacing.

The following table lists the options and values to configure a PLL on a Stratix III or Stratix IV device to clock an ALTLVDS IP core.

Table 5.  Options to Configure a PLL on a Stratix III or Stratix IV Device

Option

Value

Which PLL type will you be using?

Left_Right PLL

How will the PLL outputs be generated?

In Source-Synchronous Compensation mode

On the Output clocks page

c0

This clock signal is the high-speed serial clock (fast clock) signal connected to the rx_inclock or tx_inclock port of the ALTLVDS IP core.

Output frequency = data rate

Phase shift = -180 degrees

Duty cycle = 50%

c1

This clock signal is the load enable signal connected to the rx_enable or tx_enable port of the ALTLVDS IP core.

Output frequency = data rate/deserialization factor

Phase shift = [(deserialization factor – 2)/deserialization factor] × 360 degrees

Duty cycle = (100/deserialization factor)%

c2

This clock signal is the slow clock signal that feeds the synchronization register of the ALTLVDS IP core.

Output frequency = data rate/deserialization factor

Phase shift = (-180/deserialization factor) degrees

Duty cycle = 50%

Related Information
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