ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Public
Document Table of Contents

Summary of PLL Output Clocks

The following table summarizes and compares properties of the clock output ports per PLL for each PLL type in the supported device families. The number of clock output ports shown in the table for each device family can be set as internal or external clock output port unless described otherwise.

Table 6.  Number of Clock Output Ports per PLL

Device Family

Top_Bottom

Left_Right

Enhanced PLL

Fast PLL

Cyclone Series PLL

Arria GX

6

4

Arria II GX

7

Stratix IV

10

7

Stratix III

10

7

Stratix II

6

4

Stratix II GX

6

4

Stratix

6

1

3

Stratix GX

6

1

3

Cyclone® 10 LP

5

Cyclone IV

5

Cyclone III

5

Cyclone II

3

Cyclone

2

2
1 Only four ports can be used as the external clock output ports.
2 Only one port can be used as the external clock output port.