ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Output Clocks

The PLL can generate a number of clock output signals depending on the PLL type and the device family that you select in the ALTPLL parameter editor. For example, in a Stratix IV device, a Left_Right PLL can generate seven clock output signals, and a Top_Bottom PLL can generate as many as 10 clock output signals. The generated clock output signals are used to clock the core or external blocks outside of the core.

The ALTPLL IP core does not have a dedicated output enable port, you can disable the PLL output. You can use the pllena signal or the areset signal to disable the PLL output counters, and thereby disable the PLL output clocks. Another possible method is to feed the PLL output clock signals to the ALTIOBUF IP core and use the enable output ports of the resulting buffers to disable the signals.