ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Parameter Settings

The parameter settings to enable the dynamic phase configuration feature are located on the PLL Reconfiguration page of the ALTPLL parameter editor.

The following figure shows the dynamic phase configuration options.

Figure 18. Dynamic Phase Configuration

Turning on Create optional inputs for dynamic phase reconfiguration enables the feature, and create these ports - phasecounterselect[3..0], phaseupdown, phasestep, scanclk, and phasedone.

Turning on Enable phase shift step resolution edit allows you to modify the phase shift step resolution value for each individual PLL output clock on its Output Clocks page.

The following figure shows the new option that appears on each output clock settings page. By default, the finest phase shift resolution value is 1/8th of the VCO period. If the VCO frequency is at the lower end of the supported VCO range, the phase shift resolution might be larger than you would prefer for your design. Use this option to fine tune the phase shift step resolution.

Figure 19. Phase Shift Step Configuration

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