ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

PLL Behavior

  • PLL lock time—Also known as the PLL acquisition time, PLL lock time is the amount of time required by the PLL to attain the target frequency and phase relationship after power-up, after a programmed output frequency change, or after a reset of the PLL. Simulation software does not model a realistic PLL lock time. Simulation shows an unrealistically fast lock time.
  • PLL resolution—The minimum frequency increment value of a PLL VCO. The value is based on the number of bits in the M and N counter.
  • PLL sample rate—The fREF sampling frequency required to perform the phase and frequency correction in the PLL. The PLL sample rate is fREF /N.