Implementing the shift_clk Design
To assign the EP1S10F780C5 device to the project and compile the project, follow these steps:
- On the Assignments menu, click Settings. The Settings dialog box appears.
- In the Category list, click Device. Select Stratix in the Device Family field.
- In the Target device section, under the Available devices list, select EP1S10F780C5.
- Click OK.
- On the Processing menu, click Start Simulation.
- When the Full Compilation was successful message box appears, click OK.
- To view how the module is implemented in the Stratix device, from the Assignments menu, click Timing Closure Floorplan.
The shift_clk design is now implemented.
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