ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Gated Lock and Self-Reset

The lock time of a PLL is defined as the amount of time required by the PLL to attain the target frequency and phase relationship after device power-up, after a change in the PLL output frequency, or after resetting the PLL.

A PLL might lose lock for a number of reasons, such as the following causes:

  • Excessive jitter on the input clock.
  • Excessive switching noise on the clock inputs of the PLL.
  • Excessive noise from the power supply can cause high output jitter and possible loss of lock.
  • A glitch or stopping of the input clock to the PLL.
  • Resetting the PLL by asserting the areset or pllena ports of the PLL.
  • An attempt to reconfigure the PLL might cause the M counter, N counter, or phase shift to change, which causes the PLL to lose lock. However, changes to the post-scale counters do not affect the PLL locked signal.
  • PLL input clock frequency drifts outside the lock range specification.
  • The PFD is disabled using the pfdena port. When this happens, the PLL output phase and frequency tend to drift outside of the lock window.

The ALTPLL IP core allows you to monitor the PLL locking process using a lock signal named locked and also allows you to set the PLL to self-reset on loss of lock.