ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Dynamic Phase Configuration

The dynamic phase configuration feature allows the output phases of individual PLL outputs to dynamically adjust relative to each other and the reference clock, without sending serial data through the scan chain of the corresponding PLL. This feature is also known as the dynamic phase stepping feature.

You can use this feature to quickly adjust the output clock phase shift in real time. This adjustment is achieved by incrementing or decrementing the VCO phase-tap selection to a C counter or to the M counter. By default, the phase is shifted by 1/8th of the VCO frequency at each step. However, you can easily modify the phase shift step resolution of the individual PLL output clock using the ALTPLL parameter editor.

For dynamic phase shifting to work correctly, the PLL must have the following ports:

  • Input ports: phasecounterselect[3..0], phaseupdown, phasestep, and scanclk
  • Output port: phasedone