ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Gated Lock

Some devices support a gated lock signal that allows you to configure a programmable 20-bit counter that holds the lock signal low for a user-specified number of input clock transitions. This is useful to eliminate the false toggling of the lock signal as the PLL begins tracking the reference clock. Gated lock allows the PLL to lock before asserting the locked signal, providing a stabilized lock signal.

An asserted locked signal indicates the PLL clock output is aligned with the PLL reference input clock. The locked signal might toggle as the PLL begins tracking the reference clock. To avoid such a false lock indication, use a gated lock signal. A gated locked signal or an ungated locked signal can feed a logic array or an output pin. When you must reset the gated counter, reset the PLL by asserting the areset signal or the pllena signal.

The following figure shows the timing waveform for gated and ungated locked signals.

Figure 11. Input and Output Ports