ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Design Example 1: Differential Clock

This design example uses the ALTPLL IP core to generate an external differential clock from an enhanced PLL. You must generate or modify clock signals to meet design specifications. When you interface to double data rate (DDR) memory, you must generate a differential SSTL clock signal for the external device. A DDR DIMM requires three pairs of differential SSTL clocks. You can use enhanced PLLs in Stratix devices to generate these clock signals.

In this example, perform the following activities:

  • Generate a 166-MHz differential SSTL external clock (ddr_clk) output from a 33.33-MHz input clock using the ALTPLL IP core and the parameter editor.
  • Implement the DDR_CLK design by assigning the EP1S10F780 device to the project and compiling the project.
  • Simulate the DDR_CLK design.