ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents


The areset signal is the reset or resynchronization input for each PLL. The device input pin or internal logic can drive the areset signal. When you assert the areset signal, all counters in the PLL, including the gated lock counter, are reset to initial values, in which the PLL output is cleared and the PLL is in the out-of-lock state. The VCO is also reset to its nominal setting. When the areset signal is deasserted, the PLL resynchronizes its input and tries to gain lock.

You should include the areset signal in your designs if any of the following conditions hold:

  • PLL reconfiguration or clock switchover is enabled in your design.
  • Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock condition.
  • The input clock to the PLL is not toggling or is unstable at power-up.
  • Assert the areset signal after the input clock is toggling while staying within the input jitter specification.