ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Simulating External Feedback Board Delay

The PLL external feedback board delay option is available for Arria GX, Cyclone, HardCopy series, Stratix, Stratix GX, Stratix II, and Stratix II GX device families only.

The functional and timing models of these devices do not support the simulation of external feedback. To simulate the external feedback mode, perform the following steps:

  1. In the Quartus® Prime software, open an existing project or create a new project.
  2. On the Assignments menu, click Assignment Editor.
  3. In the Category bar, under Timing, click All.
  4. In the spreadsheet, double-click an empty row in the To cell and either type in the pin name or click the arrow to use the Node Finder to search for the external feedback input pin.
  5. Double-click the Assignment Name cell, and select PLL External Feedback Board Delay.
  6. In the Value cell, double-click and type the amount of time for the signal to propagate between the external clock output pin through the trace on the board and into the external feedback input pin.
  7. Simulate your design.
The behavioral models for the ALTPLL IP core reside in the \quartus\eda\sim_lib directory. The altera_mf.vhd file contains the VHDL behavioral models and the altera_mf.v file contains the Verilog HDL behavioral models. The behavioral model does not perform parameter error checking, so you must specify valid values.