ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

Parameter Settings

To enable the locked signal, and the self-reset feature in the ALTPLL IP core, use the parameter settings on the Scan/Inputs/Lock or Inputs/Lock page of the ALTPLL parameter editor.

The following figure shows the related options in the Scan/Inputs/Lock or Inputs/Lock page for an Arria II GX device. Note that the options are device-dependent and what you see may differ.

Figure 12. Lock Output Options

Turning on Create 'locked' output creates an output port named locked in the ALTPLL IP core.

Turning on Enable self-reset on loss of lock enables the self-reset feature.

In devices that support gated lock, another option appears on the page, which is the Hold 'locked' output option. Turning on this option enables the gated lock circuitry to gate the locked signal. You must specify the number of PLL input clock cycles to hold the locked signal low after the PLL is initialized. This value is used by the gated lock counter. The value ranges from 1 to 1,048,575 clock cycles.

The following figure shows the Hold Locked Output option.

Figure 13. Hold Locked Output Option