AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

SoC HPS Execute-in-Place (XiP) Variant

The DOC_FE2H_CVSX_XiP variant is an example of a minimal motor control project for Cyclone V SoCs requiring no external memory. Execute-in-Place (XiP) refers to executing the application directly from flash memory (quad serial peripheral interface (QSPI) in this case). If the code footprint is small enough to fit entirely in the L2 cache, performance is similar to that achieved with external DDR memory and L2 cache. The variant uses on-chip RAM (OCRAM) for data storage. You may implement additional memory in the FPGA but do not use it for frequently accessed data. Accesses to this memory incur the latency through the HPS2FPGA bridges. The XiP variant uses FPGA memory for debug data to be shared with the System Console debug GUI.

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