Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.3.2.1. Receive Path Blocks

The Interlaken IP core receive data path has the following four main functional blocks:
  • RX PMA
  • RX PCS
  • RX MAC
  • RX Regroup Block
Figure 11. Interlaken IP Core Receive Path Blocks for L-, H- and E-Tile NRZ Mode Device VariationsThe figure illustrates the eight word data transfer scenario. This figure uses the following conventions:
  • n = Number of calender pages
  • m = Number of lanes
Figure 12. Interlaken IP Core Receive Path Blocks for E-Tile PAM4 Mode Device VariationsThe figure illustrates the eight word data transfer scenario. This figure uses the following conventions:
  • n = Number of calender pages
  • m = Number of lanes
The Interlaken IP core receive data path has the following four main functional blocks:
  • RX PMA
  • RX PCS
  • RX MAC
  • RX Regroup Block

RX PMA

The Interlaken IP core RX PMA deserializes data that the IP core receives on the serial lines of the Interlaken link. RX PMA contains RS FEC block in PAM4 mode of E-tile devices and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each RS FEC block serves four FEC channels in the aggregate mode.

RX PCS

In Intel® Stratix® 10 L- and H- Tile device variations, RX PCS logic is an embedded hard macro and does not consume FPGA soft logic elements. The FPGA soft logic implements RX PCS in E-tile devices. In PAM4 mode, the E-tile device variations contain a soft logic transcoder block to work with RS FEC of the RX PMA. The Interlaken IP core RX PCS block performs the following functions to retrieve the data:
  • Detects word lock and word synchronization.
  • Checks running disparity.
  • Reverses gear-boxing and 64/67B encoding.
  • Descrambles the data.
  • Delineates meta frame boundaries.
  • Performs CRC32 checking.
  • Sends lane status information to the calendar and status blocks, if Include in-band flow control functionality is turned on.
  • Performs asynchronous operations and receiver alignment using RX Align FIFO.
  • Performs the Interlaken inverse transcoding function on the data received from the RX RS FEC (544, 514) in E-tile PAM4 mode device variations.

For more information about error conditions, refer to the ILKN_FEC_XCODER_TX_ILLEGAL_STATE (offset 0x80) and ILKN_FEC_XCODER_RX_UNCOR_FECCW (offset 0x81) registers. You can also obtain more details from the FEC status, FEC correctable and uncorrectable registers documented in the RS-FEC Registers section of the E-Tile Transceiver PHY User Guide.

RX MAC

To recover a packet or burst, the RX MAC takes data from each of the PCS lanes and reassembles the packet or burst. The Interlaken IP core RX MAC performs the following functions:
  • Data de-striping, including lane alignment and burst assembly from the PCS lanes.
  • CRC24 validation.
  • Calendar recovery, if Include in-band flow control functionality is turned on.

RX Regroup Block

The Interlaken IP core RX regroup block translates the IP core internal data format to the outgoing user application data irx_dout_words format.

For details on transceiver initialization, please refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide or the E-Tile Transceiver PHY User Guide.

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