5.5. Reconfiguration Interface Signals
|Signal Name||Feature Support||Width (Bits)||I/O Direction||Description|
|reconfig_clk||ILK and ILA||1||Input||Intel® Stratix® 10 transceiver reconfiguration interface clock.|
|reconfig_reset||1||Input||Active-high synchronous reset. Assert this signal to reset the Intel® Stratix® 10 transceiver reconfiguration interface.|
|reconfig_read||1||Input||Read access to the Intel® Stratix® 10 hard PCS registers.|
|reconfig_write||1||Input||Write access to the Intel® Stratix® 10 hard PCS registers.|
Refer to the table below to find out the value of RECONF_ADDR:
|Input||Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed.
The E-tile PAM4 mode IP variations customize the most significant bit (MSB) of the reconfig_address as follows:
In E-tile NRZ mode IP variations, the MSB of reconfig_address (e.g., bit  for 12 lanes NRZ) is always unused while the remaining bits are used to access PMA registers.
|reconfig_writedata||32||Input||When reconfig_write is high, reconfig_writedata holds valid write data.|
|reconfig_readdata||32||Output||After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.|
|reconfig_waitrequest||1||Output||Busy signal for reconfig_readdata.|
For information on PMA and RS-FEC registers of the E-tile transceiver PHY, refer to the PMA Register Map section.
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