Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

5.5. Reconfiguration Interface Signals

The reconfiguration interface signals are available for the AVMM interface.
Table 32.  Reconfiguration Interface Signals
Signal Name Feature Support Width (Bits) I/O Direction Description
reconfig_clk ILK and ILA 1 Input Intel® Stratix® 10 transceiver reconfiguration interface clock.
reconfig_reset 1 Input Active-high synchronous reset. Assert this signal to reset the Intel® Stratix® 10 transceiver reconfiguration interface.
reconfig_read 1 Input Read access to the Intel® Stratix® 10 hard PCS registers.
reconfig_write 1 Input Write access to the Intel® Stratix® 10 hard PCS registers.
reconfig_address
  • RECONF_ADDR+11 (For L-Tile and H-Tile device variations)
  • RECONF_ADDR+20 (For E-tile device variations)
Refer to the table below to find out the value of RECONF_ADDR:
Lanes RECONF_ADDR (Bits)
4 2
6 3
8 3
10 4
12 4
Input Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed.
The E-tile PAM4 mode IP variations customize the most significant bit (MSB) of the reconfig_address as follows:
  • There are three Native PHY available in an E-tile PAM4 mode Interlaken design. The reconfig_address[22:21] bits select which native PHY to access as below:
    • 2'b00- 1st Naive PHY
    • 2'b01- 2nd Native PHY
    • 2'b10- 3rd Native PHY
    • 2'b11- Reserved
  • The reconfig_address[23] bit selects RS-FEC registers when set to 1 and PMA registers when set to 0.
  • The active bits within the reconfig_address[20:0] differs when you access RS-FEC registers as compared to PMA registers. Refer to the PMA Register Map section of the E-tile Transceiver PHY User Guide for more information on this.

In E-tile NRZ mode IP variations, the MSB of reconfig_address (e.g., bit [23] for 12 lanes NRZ) is always unused while the remaining bits are used to access PMA registers.

reconfig_writedata 32 Input When reconfig_write is high, reconfig_writedata holds valid write data.
reconfig_readdata 32 Output After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.
reconfig_waitrequest 1 Output Busy signal for reconfig_readdata.
For information on Intel Stratix 10 L- and H-tile Transceiver PHY registers, refer to the Logical View of the L-tile/H-tile Transceiver Registers section.

For information on PMA and RS-FEC registers of the E-tile transceiver PHY, refer to the PMA Register Map section.

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