Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022

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5.5. Reconfiguration Interface Signals

The reconfiguration interface signals are available for the AVMM interface.
Table 32.  Reconfiguration Interface Signals
Signal Name Feature Support Width (Bits) I/O Direction Description
reconfig_clk ILK and ILA 1 Input Intel® Stratix® 10 transceiver reconfiguration interface clock.
reconfig_reset 1 Input Active-high synchronous reset. Assert this signal to reset the Intel® Stratix® 10 transceiver reconfiguration interface.
reconfig_read 1 Input Read access to the Intel® Stratix® 10 hard PCS registers.
reconfig_write 1 Input Write access to the Intel® Stratix® 10 hard PCS registers.
  • RECONF_ADDR+11 (For L-Tile and H-Tile device variations)
  • RECONF_ADDR+20 (For E-tile device variations)
Refer to the table below to find out the value of RECONF_ADDR:
Lanes RECONF_ADDR (Bits)
4 2
6 3
8 3
10 4
12 4
Input Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed.
The E-tile PAM4 mode IP variations customize the most significant bit (MSB) of the reconfig_address as follows:
  • There are three Native PHY available in an E-tile PAM4 mode Interlaken design. The reconfig_address[22:21] bits select which native PHY to access as below:
    • 2'b00- 1st Naive PHY
    • 2'b01- 2nd Native PHY
    • 2'b10- 3rd Native PHY
    • 2'b11- Reserved
  • The reconfig_address[23] bit selects RS-FEC registers when set to 1 and PMA registers when set to 0.
  • The active bits within the reconfig_address[20:0] differs when you access RS-FEC registers as compared to PMA registers. Refer to the PMA Register Map section of the E-tile Transceiver PHY User Guide for more information on this.

In E-tile NRZ mode IP variations, the MSB of reconfig_address (e.g., bit [23] for 12 lanes NRZ) is always unused while the remaining bits are used to access PMA registers.

reconfig_writedata 32 Input When reconfig_write is high, reconfig_writedata holds valid write data.
reconfig_readdata 32 Output After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.
reconfig_waitrequest 1 Output Busy signal for reconfig_readdata.
For information on Intel Stratix 10 L- and H-tile Transceiver PHY registers, refer to the Logical View of the L-tile/H-tile Transceiver Registers section.

For information on PMA and RS-FEC registers of the E-tile transceiver PHY, refer to the PMA Register Map section.