Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.4.1.1. Transmit Path Blocks

The Interlaken Look-aside mode transmit data path has the following three main functional blocks:
  • TX MAC
  • TX PCS
  • TX PMA
Figure 16. Interlaken Look-aside IP Core Transmit Path Blocks for L- , H-, and E-Tile NRZ Mode Device VariationsThe figure illustrates the eight word data transfer scenario.
Figure 17. Interlaken Look-aside IP Core Transmit Path Blocks for E-Tile PAM4 Mode Device VariationsThe figure illustrates the eight word data transfer scenario.

TX MAC

The Interlaken Look-aside IP core TX MAC performs the following functions:
  • Populates burst and idle control words in the incoming data stream to align with the Interlaken Look-aside protocol.
  • Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
  • Calculates and inserts CRC24 bits in all burst and idle words.

TX PCS

In E-tile device variations, the FPGA soft logic implements TX PCS. In PAM4 mode, the E-tile device variations contain a soft logic transcoder block to work with RS FEC (544, 514) of the TX PMA. The Interlaken IP core TX PCS block performs the following functions for each lane:
  • Inserts the meta frame words in the incoming data stream.
  • Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
  • Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
  • Performs 64B/67B encoding.
  • Performs asynchronous operations and transmission lane alignment using TX Align FIFO.
  • Performs the Interlaken transcoding function to support the RS FEC (544, 514) of the TX PMA in PAM4 mode applications.

TX PMA

The Interlaken IP core TX PMA serializes the data and sends it out on the Interlaken link. TX PMA contains RS FEC block in PAM4 mode of E-tile devices and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each RS FEC block serves four FEC channels in the aggregate mode.
Note: Normal operation of Interlaken (2nd Generation) Intel® FPGA IP produces skew of 131 UI or smaller. There is a theoretical chance that on a given reset, channel-to-channel skew can be as much as 259 UI. The Interlaken (2nd Generation) Intel® FPGA IP supports significantly more than 259 UI skew, as can many products in the market. If your Interlaken receiver cannot tolerate a skew beyond 134 UI transmit skew in the Interlaken interop guide, please contact Intel Premier Support.

Pin out your Interlaken IP core to exist within a single tile of Intel® Stratix® 10 device. If you have to pin out your core across multiple tiles, please contact Intel Premier Support.

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