Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.3.2.3.1. Example With Errors and In-Band Calendar Bits

This example illustrates the expected behavior of the Interlaken IP core application interface receive signals during a packet transfer with CRC or other errors. In the example, the errored packet transfer is followed by two idle cycles and a non-errored packet transfer.
Figure 13. Interlaken IP Core Receiver Side With irx_err ErrorsThis figure illustrates the attempted transfer of a 179-byte packet on the RX user data transfer interface to channel 2, after the Interlaken IP core receives the packet on the Interlaken link and detects corruption. Following the errored packet, the IP core transfers an uncorrupted packet to channel 3.

In cycle 1, the Interlaken IP core asserts irx_sop[1] when data is ready on irx_dout_words. When the Interlaken IP core asserts irx_sop[1], it also asserts the correct value on irx_chan to tell the application the data channel destination of the data. In this example, the value 2 on irx_chan tells the application that the data should be sent to channel number 2.

During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled with data value d2), the Interlaken IP core holds the value of irx_num_valid[7:4] at 4'b1000. In the following clock cycle, labeled with data value d3, the Interlaken IP core holds the following values on critical output signals:
  • irx_num_valid[7:4] at the value of 4'b0111 to indicate the current data symbol contains seven 64-bit words of valid data.
  • irx_eopbits[3] high to indicate the current cycle is an EOP cycle.
  • irx_eopbits[2:0] at the value of 3'b011 to indicate that only three bytes of the final valid data word are valid data bytes.
This signal behavior, in the absence of the irx_err flag, would correctly transfer a data packet with the total packet length of 179 bytes from the Interlaken IP core. However, the Interlaken IP core marks the burst as errored by asserting the irx_err signal, even though the irx_eopbits signal would appear to indicate the packet is valid.

The application is responsible for discarding the errored packet when it detects that the IP core has asserted the irx_err signal. Following the corrupted packet, the IP core waits two idle cycles and then transfers a valid 139-byte packet.

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