5.4. Management Interface Signals
|Signal Name||Feature Support||Width (Bits)||I/O Direction||Description|
|mm_clk||ILK and ILA||1||Input||Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz–125 MHz.|
Read access to the register ports.
Write access to the register ports.
Address to access the register ports.
When mm_rdata_valid is high, mm_rdata holds valid read data.
Valid signal for mm_rdata.
When mm_write is high, mm_wdata holds valid write data.
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