Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

5.7. External PLL Interface Signals

The external PLL interface signals are only available in the L-Tile and H-Tile device variations. For the E-tile device variations, tie the input signals low. The output signals can float.

Table 38.  ATX PLL Interface Signals
Signal Name Feature Support Width (Bits) I/O Direction Description
tx_pll_locked ILK and ILA 1 Input PLL-locked indication from external TX PLL.

This signal is only available in Intel® Stratix® 10 H-tile device variations.

tx_pll_cal_busy 1 Input PLL-busy indication from external TX PLL.

This signal is only available in Intel® Stratix® 10 H-tile device variations.

tx_serial_clk NUM_LANES Input High-speed clock for transceiver channel, provided from external TX PLL

This signal is only available in Intel® Stratix® 10 H-tile device variations.

tx_pll_powerdown 1 Output Output signal from the IP core internal reset controller. The IP core asserts this signal to tell the external PLLs to power down.

This signal is only available in Intel® Stratix® 10 H-tile device variations.

mac_pll_locked 1 Input Lock indicator for the PLL that generates mac_clkin. This signal is only available in PAM4 mode of E-Tile device variations.

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