Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.26 22.1 20.0.3 Corrected the description of PCS_BASE register.
2022.04.04 22.1 20.0.3
  • Removed support for ModelSim* SE simulator.
  • Updated the Round-trip Latency and Performance and Resource Utilization numbers.
2021.10.04 21.3 20.0.1
  • Added support for QuestaSim* simulator.
  • Removed support for NCSim simulator.
2021.02.24 20.4 20.0.1
  • Added the following parameters:
    • Preserve unused transceiver channels for PAM4
    • Reference clock frequency for preserved channels
  • Added the pll_ref_clk[1] signal description in section: Clock and Reset Interface Signals.
  • Clarified the information about TX skew in section: Transmit Path Blocks.
2020.10.16 20.3 20.0.0
  • Changed the data rates support from 25.3 Gbps to 25.28 Gbps and 25.8 Gbps to 25.78 Gbps.
  • The IP now supports new data rate 25.78125 Gbps.
  • Updated Table: IP Supported Combinations of Number of Lanes and Data Rates to clarify the supported data rate/number of lanes combination for Interlaken look-aside IP variations.
  • Updated the data rate support information in the following sections:
    • Features
    • Flexible Lanes Support
    • Round-trip Latency
    • Parameter Settings
  • Updated Table: IP Theoretical Raw Aggregate Bandwidth for 25.28, 25.78, and 25.78125 Gbps data rates.
  • Updated Performance and Resource Utilization section for Intel® Quartus® Prime software version 20.3.
  • Added transceiver reference clock frequency for the 25.78125 Gbps data rate in the following sections:
    • Main Parameters
    • Clock and Reset Interface Signals
  • Updated section Release Information.
  • Updated Figure: IP Parameter Editor.
  • Clarified that Number of Segments parameter is grayed out for Interlaken Look-aside IP variations in Table: User Data Interface.
  • Updated the description of the reconfig_address signal for the E-tile PAM4 mode IP variations in Table: Reconfiguration Interface Signals.
2020.06.22 20.2 19.3.0
  • The IP now supports Interlaken Look-aside feature.
  • Updated the following section to include Interlaken Look-aside information:
    • Figure: Typical Interlaken Application
    • Features
    • Performance and Resource Utilization
    • Figure: IP Parameter Editor
    • Figure: Interlaken (2nd Generation) Intel FPGA IP High Level System Overview
  • The IP now supports 10x12.5 Gbps combination in H- and E-tile IP core variations.
  • Clarified the user clock frequency values for H- and E-tile device variations in Table: Recommended User Clock Frequency.
  • Added new parameter Enable Interlaken Look-aside mode in chapter: Parameter Settings.
  • Updated values of pll_ref_clk frequencies for H- and E-tile device variations in chapter: Parameter Settings.
  • Added new section PMA Adaptation Flow.
  • Added following new sections:
    • High Level Data Path Flow for Interlaken Look-aside Mode
    • Interlaken Look-aside Mode
  • Clarified that the design example provides logic to include out-of-band flow control functionality.
  • Modified Figure: IP Core Interface Signals to include new signals related to Interlaken Look-aside.
  • Added new signals related to Interlaken Look-aside in Chapter: Interface Signals and differentiate availability of the signals in two different modes of the IP.
  • Added new table Section: Clock and Reset Interface Signals to include frequency values for clk_tx_common.
  • Removed itx_hungry signal.
  • Removed Table: Transceiver Interface Signals.
2019.09.27 19.3 19.2.1
  • Added public support for Intel Agilex E-tile variants.
  • Updated Performance and Resource Utilization for L-, H-, and E-tile device variations.
  • Added topic Round trip Latency.
  • Renamed and updated the Figure: Interlaken (2nd Generation) Intel FPGA IP High-Level System Overview.
2019.07.01 19.2 19.2 Made the following changes:
  • Added EAP support for Intel Agilex E-tile variants.
  • Added information about the PMA Adaptation parameters available for the E-tile transceiver.
  • Added topic on preserving performance in unused E-tile transceivers.
  • Updated Performance and Resource Utilization for E-tile transceivers.
  • Added definitions of tx_pin_n and rx_pin_n signals. The PAM4 loopback example design uses these signals.
  • Added Interlaken Clock Domains figure to IP Core Clocks topic.
2018.12.24 18.1.1 18.1.1
  • Updated section Features.
  • Added the new supported combinations of number of lanes and data rates in Table: IP Core Supported Combinations of Number of Lanes and Data Rate.
  • Added new section Flexible Lanes Support.
  • Added new parameter Number of Segment in Table: Interlaken IP Core Parameter Settings: IP Tab.
  • Added new section Multi-Segment Mode.
  • Updated section Transmit User Interface Signals and Receive User Interface Signals.
  • Added the following new signals in Table: Transmit User Interface Signals:
    • itx_eob1
    • itx_eopbits1
    • itx_chan1
  • Added the following new signals in Table: Receive User Interface Signals:
    • irx_eob1
    • irx_eopbits1
    • irx_chan1
    • irx_err1
    • irx_err
  • Added new signal mac_pll_locked in Table: ATX PLL Interface Signals.
2018.09.24 18.1 18.1
  • Renamed the document title as Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide
  • Added VHDL simulation model and testbench support for Interlaken (2nd Generation) IP core.
  • Added information about additional clock mac_clkin for E-tile PAM4 mode variations in Adding the External PLL section and updated the description about this signal in Table: Interlaken IP Core Clocks.
  • Added new Interlaken IP core block diagrams for E-tile PAM4 mode in High Level System Flow section.
  • Made the following changes in Transmit Path Blocks section:
    • Added Figure: Interlaken IP Core Transmit Path Blocks for E-tile PAM4 Mode Device Variations
    • Updated information in TX MAC, TX PCS, and TX PMA sections for E-tile device variations.
  • Made the following changes in Receive Path Blocks section:
    • Added Figure: Interlaken IP Core Transmit Path Blocks for E-tile PAM4 Mode Device Variations
    • Updated information in RX MAC, RX PCS, and RX PMA sections for E-tile device variations.
  • Added new section Performance to showcase how to calculate bandwidth performance.
  • Updated signal description in Transmit User Interface Signals and Receive User Interface Signals.
  • Clarified the AVMM interface signals are available for the H-, L- and E-tile device variations.
  • Added steps to turn on internal serial loopback mode in IP core variations that target an E-tile devices.
  • Added following new registers related to E-tile device variations in Register Map section:
    • TX_READY_XCVR
    • RX_READY_XCVR
    • ILKN_FEC_XCODER_TX_ILLEGAL_STATE
    • ILKN_FEC_XCODER_RX_ILLEGAL_STATE
2018.07.16 18.0.1 18.0.1
  • Added support for the devices with E-tile transceivers.
  • Added 53.125 Gbps data rate support for Intel® Stratix® 10 E-tile devices in PAM4 mode.
  • Added the new supported combinations of number of lanes and data rates in Table: IP Core Supported Combinations of Number of Lanes and Data Rate.
  • Updated the Table: Performance and Resource Utilization for E-tile devices in NRZ and PAM4 mode.
  • Added new parameter XCVR Mode in Table: Interlaken IP Core Parameter Settings: IP Tab.
  • Added new Transceiver reference clock frequency values for 25.3, 25.8, and 26.5625 Gbps data rate in the Table: Interlaken IP Core Parameter Settings: IP Tab and Table: Clock and Reset Interface Signals.
  • Added clock signal mac_clkin in Table: Interlaken IP Core Clocks for Intel® Stratix® 10 E-tile PAM4 devices.
  • Updated Table: IP Core Register Map for E-tile devices.
2018.05.07 18.0 18.0
  • Renamed the document as Interlaken (2nd Generation) Intel FPGA IP User Guide
  • Added new 25.8 Gbps data rate support for number of lanes 6 and 12.
  • Added Cadence Xcelium Parallel simulator support.
  • Added new section Integrating Your IP Core in Your Design explaining how to make appropriate pin assignments and add external PLL.
  • Added the Transceiver reference clock frequency for 25.8 Gbps data rate in the Table: Interlaken IP Core Parameter Settings: IP Tab and Table: Clock and Reset Interface Signals.
  • Modified default setting value for the Tx Scrambler Seed parameter in Table: Interlaken IP Core Parameter Settings: IP Tab
  • Clarified the direction of the IP core clocks in Table: Interlaken IP Core Clocks.
Date Version Changes
November 2017 2017.11.06
  • Updated for Intel® Quartus® Prime Pro Edition 17.1 release.
  • Updated support for the Intel® Stratix® 10 devices with L-Tile and H-Tile transceivers in Table: IP Core Supported Combinations of Number of Lanes and Data Rate.
  • Added the resource utilization numbers for 25.3 Gbps data rate in Table: FPGA Resource Utilization.
  • Added support for Cadence NCSim simulator.
  • Added new parameter Transceiver Tile in Table: Interlaken IP Core Parameter Settings: IP Tab.
  • Removed 412.5 MHz pll_ref_clk frequency support for 25.3 Gbps data rate in Table: Clock and Reset Interface Signals.
  • Added new signal nad_cntr_inc in Table: Real-Time Receiver Status Signals.
Added the resource utilization numbers for 25.3May 2017 2017.05.08
  • Updated the resource utilization in Table: FPGA Resource Utilization.
  • Added the new supported combinations of number of lanes and data rate (6x25.3G and 12x25.3G) in Table: IP Core Supported Combinations of Number of Lanes and Data Rate
  • Corrected the steps for Specifying the IP Core Parameters and Options.
  • Added the transceiver reference clock frequency for 25.3 Gbps data rate in the Table: Interlaken IP Core Parameter Settings and Table: Clock and Reset Interface Signals.
December 2016 2016.12.19
  • Dynamic reconfiguration support is now available for Intel® Stratix® 10 devices.
  • Added a new parameter VCCR_GXB and VCCT_GXB supply voltage for the transceivers in the table: Interlaken IP Core Parameter Settings.
August 2016 2016.08.08 Initial version for Quartus Prime Pro – Stratix 10 Edition Beta software.

Did you find the information on this page useful?

Characters remaining:

Feedback Message