Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.4.2.1. Receive Path Blocks

The Interlaken Look-aside mode receive data path has the following four main functional blocks:
  • RX Regroup
  • RX MAC
  • RX PCS
  • RX PMA
Figure 18. Interlaken Look-aside IP Core Receive Path Blocks for E-Tile NRZ Mode Device VariationsThe figure illustrates the eight word data transfer scenario. This figure uses the following conventions:
  • m= Number of lanes
Figure 19. Interlaken Look-aside IP Core Receive Path Blocks for E-Tile PAM4 Mode Device VariationsThe figure illustrates the eight word data transfer scenario. This figure uses the following conventions:
  • m= Number of lanes

RX Regroup

The Interlaken Look-aside IP core RX regroup block translates the IP core internal data format to the outgoing user application data

RX MAC

To recover a packet or burst, the RX MAC takes data from each of the PCS lanes and reassembles the packet or burst. The Interlaken IP core RX MAC performs the following functions:
  • Data de-striping, including lane alignment and burst assembly from the PCS lanes.
  • CRC24 validation.

RX PCS

The FPGA soft logic implements RX PCS in E-tile devices. In PAM4 mode, the E-tile device variations contain a soft logic transcoder block to work with RS FEC of the RX PMA. The Interlaken IP core RX PCS block performs the following functions to retrieve the data:
  • Detects word lock and word synchronization.
  • Checks running disparity.
  • Reverses gear-boxing and 64/67B encoding.
  • Descrambles the data.
  • Delineates meta frame boundaries.
  • Performs CRC32 checking.
  • Performs asynchronous operations and receiver alignment using RX Align FIFO.
  • Performs the Interlaken inverse transcoding function on the data received from the RX RS FEC (544, 514) in E-tile PAM4 mode device variations.

For more information about error conditions, refer to the ILKN_FEC_XCODER_TX_ILLEGAL_STATE (offset 0x80) and ILKN_FEC_XCODER_RX_UNCOR_FECCW (offset 0x81) registers. You can also obtain more details from the FEC status, FEC correctable and uncorrectable registers documented in the RS-FEC Registers section of the E-Tile Transceiver PHY User Guide.

RX MAC

To recover a packet or burst, the RX MAC takes data from each of the PCS lanes and reassembles the packet or burst. The Interlaken IP core RX MAC performs the following functions:
  • Data de-striping, including lane alignment and burst assembly from the PCS lanes.
  • CRC24 validation

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