Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

2.3. Specifying the IP Core Parameters and Options

The IP parameter editor allows you to quickly configure your custom IP variation. Perform the following steps to specify IP core options and parameters in the Intel® Quartus® Prime Pro Edition software.

The Interlaken IP is not supported in Platform Designer. You must use the IP Catalog accessible from the Intel® Quartus® Prime Pro Edition Tools menu. The Interlaken IP does not support VHDL simulation models. You must specify the Verilog HDL for both synthesis and simulation models.

IP Parameter Editor
  1. In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
  2. Select the device family either Stratix 10 (GX/SX/MX/TX) or Agilex (FB/FA) as your target device.
  3. In the IP Catalog (Tools > IP Catalog), locate and double-click Interlaken (2nd Generation) Intel® FPGA IP . The New IP Variant window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  5. Click Create. The parameter editor appears.
  6. On the IP tab, specify the parameters and options for your IP variation, including one or more of the following. Refer to Parameter Settings for information about specific IP core parameters.
    • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
    • Specify options for processing the IP core files in other EDA tools.
  7. Click Generate HDL. The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  9. Optionally, click Generate Example Design tab in the parameter editor to generate a demonstration testbench and example design for your IP core variation.
    Note: To generate the demonstration testbench and example design, you must specify Verilog HDL for both synthesis and simulation models.
  10. Click Finish. The parameter editor adds the top-level .ip file to the project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  11. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

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