Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

7.1. Internal Serial Loopback Mode

The Interlaken IP core supports an internal TX to RX serial loopback mode.
To turn on internal serial loopback in L- and H-tile device variations:
  • Reset the IP core by asserting and then deasserting the active low reset_n signal.
  • After reset completes, set the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all ones.
    Note: Refer to IP Core Reset for information about the required wait period for register access.
  • Monitor the RX lanes aligned bit (bit 1) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.
To turn off internal serial loopback:
  • Reset the IP core by asserting and then deasserting the active low reset_n signal. Resetting the IP core sets the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all zeros.
  • Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in normal operational mode.
To turn on internal serial loopback in E-tile device variations:
  • Reconfigure the PMA settings by using PMA attribute code 0x0008 of the transceiver PHY reconfiguration interface.
    1. Write 0x84[7:0] = 0x01
    2. Write 0x85[7:0] =0x01
    3. Write 0x86[7:0] = 0x08
    4. Write 0x87[7:0] = 0x00
    5. Write 0x90[0] = 1’b1
    6. Read 0x8A[7]. It should be 1
    7. Read 0x8B[0] until it changes to 0
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value
  • Perform the initial RX equalizer adaption calibration steps. Refer to the PMA Receiver Equalization Adaption Usage Model section in the E-Tile Transceiver PHY User Guide.
  • Reset the IP core by asserting and then deasserting the active low reset_n signal.
  • Monitor the RX lanes aligned bit (bit 1) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.
To turn off internal serial loopback:
  • Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in normal operational mode.
  • Reconfigure the PMA settings to turn off the serial loop back mode by using PMA attribute code 0x0008 of the transceiver PHY reconfiguration interface..
    1. Write 0x84[7:0] = 0x00
    2. Write 0x85[7:0] =0x00
    3. Write 0x86[7:0] = 0x08
    4. Write 0x87[7:0] = 0x00
    5. Write 0x90[0] = 1’b1
    6. Read 0x8A[7]. It should be 1
    7. Read 0x8B[0] until it changes to 0
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value

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