Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.2. IP Clocks

Table 21.  Interlaken IP Core Clocks

Clock Name

Device

Direction

Description

pll_ref_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Input

Reference clock for the RX CDR PLL.

tx_serial_clk[NUM_LANES–1:0] Intel® Stratix® 10 L- and H-Tile Input

Clocks for the individual transceiver channels in Interlaken IP.

rx_usr_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Input
Clock for the receive application interface.
Note: This clock is not present in Interlaken Look-aside IP core variations.
tx_usr_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Input

Clock for the transmit application interface.

Note: This clock is not present in Interlaken Look-aside IP core variations.
reconfig_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Input

Management clock for hard PCS register access, including access for transceiver reconfiguration and testing features. Refer to the appropriate Transceiver PHY User Guide for the frequency of the reconfig_clk.

mm_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Input

Management clock for Interlaken IP core register access. Intel® recommends that you use the mm_clk value same as the reconfig_clk.

clk_tx_common
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Output Transmit PCS common lane clock driven by the SERDES transmit PLL.
clk_rx_common
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ E-tile
Output Receive PCS common lane clock driven by the CDR in transceiver.
mac_clkin Intel® Stratix® 10 and Intel® Agilex™ E-Tile (PAM4 only) Input

This signal must be driven by a PLL. This PLL must use the same clock source that drives the pll_ref_clk .

The value of mac_clkin signal is 396 MHz.

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