Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.4. High Level Data Path Flow for Interlaken Look-aside Mode

The Interlaken Look-aside mode consists of two paths:
  • Interlaken Look-aside TX path
  • Interlaken Look-aside RX path
Each path includes MAC, PCS, and PMA blocks. The PCS blocks are implemented in hard IP.
Figure 14. Interlaken Look-aside Mode Block Diagram for E-Tile NRZ Mode Device VariationsThe figure illustrates the eight word data transfer scenario. This figure uses the following conventions:
  • m = Number of lanes
Figure 15. Interlaken Look-aside Mode Block Diagram for E-Tile PAM4 Mode Device VariationsThe figure illustrates the eight word data transfer scenario. This figure uses the following conventions:
  • m = Number of lanes

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