18.104.22.168. Transmit Path Blocks
- TX Transmit Buffer
- TX MAC
- TX PCS
- TX PMA
TX Transmit Buffer
The Interlaken IP core TX transmit buffer aligns the incoming user application data, itx_din_words in the IP core internal format.
- Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet interleaving in the Interlaken protocol.
- Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
- Calculates and inserts CRC24 bits in all burst and idle words.
- Inserts calendar data in all burst and idle words, if you configure in-band flow control.
- Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0.
- Stripes and de-stripes between the user data (data width) and the number of lanes. Refer to Table 2: IP Core Theoretical Raw Aggregate Bandwidth in this document for more information on supported combinations.
- Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width.
- Inserts the meta frame words in the incoming data stream.
- Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
- Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
- Performs 64B/67B encoding.
- Performs asynchronous operations and transmission lane alignment using TX Align FIFO.
- Performs the Interlaken transcoding function to support the RS FEC (544, 514) of the TX PMA in PAM4 mode applications.
For L-tile and H-tile variants, soft PCS bonding is implemented, PMA and PCS bonding is not enabled. The TX skew is about 39 UI.
Pin out your Interlaken IP core to exist within a single tile of Intel® Stratix® 10 device. If you have to pin out your core across multiple tiles, please contact Intel Premier Support.
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