Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks TX Transmit Buffer TX MAC TX PCS TX PMA 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

4.3.1.1. Transmit Path Blocks

The Interlaken IP core transmit data path has the following four main functional blocks:
  • TX Transmit Buffer
  • TX MAC
  • TX PCS
  • TX PMA
Figure 9. Interlaken IP Core Transmit Path Blocks for L- , H- and E-Tile NRZ Mode Device VariationsThe following figure illustrates the 8-word data transfer scenario:
Figure 10. Interlaken IP Core Transmit Path Blocks for E-Tile PAM4 Mode Device VariationsThe following figure illustrates the 8-word data transfer scenario:

TX Transmit Buffer

The Interlaken IP core TX transmit buffer aligns the incoming user application data, itx_din_words in the IP core internal format.

TX MAC

The Interlaken IP core TX MAC performs the following functions:
  • Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet interleaving in the Interlaken protocol.
  • Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
  • Calculates and inserts CRC24 bits in all burst and idle words.
  • Inserts calendar data in all burst and idle words, if you configure in-band flow control.
  • Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0.
  • Stripes and de-stripes between the user data (data width) and the number of lanes. Refer to Table 2: IP Core Theoretical Raw Aggregate Bandwidth in this document for more information on supported combinations.
  • Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width.

TX PCS

In L- and H-tile device variations, TX PCS logic is an embedded hard macro and does not consume FPGA soft logic elements. In E-tile device variations, the FPGA soft logic implements TX PCS. In PAM4 mode, the E-tile device variations contain a soft logic transcoder block to work with RS FEC (544, 514) of the TX PMA. The Interlaken IP core TX PCS block performs the following functions for each lane:
  • Inserts the meta frame words in the incoming data stream.
  • Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
  • Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
  • Performs 64B/67B encoding.
  • Performs asynchronous operations and transmission lane alignment using TX Align FIFO.
  • Performs the Interlaken transcoding function to support the RS FEC (544, 514) of the TX PMA in PAM4 mode applications.

TX PMA

The Interlaken IP core TX PMA serializes the data and sends it out on the Interlaken link. TX PMA contains RS FEC block in PAM4 mode of E-tile devices and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each RS FEC block serves four FEC channels in the aggregate mode.
Note: For E-tile variants: The Interlaken Alliance Interoperability Recommendations v1.11 section 2.5.2 suggests doubling the skew budget from 107UI to 214UI for data lane bit rates higher than 6.25Gbps. TX skew of the Interlaken (2nd Generation) Intel® FPGA IP on Intel® Stratix® 10 or Intel® Agilex™ E-Tile devices is usually less than 130UI. There is a theoretical possibility that on a given reset, channel-to-channel skew can be as much as 258 UI. This is not observed in practical scenerio. A reset of the Interlaken (2nd Generation) Intel® FPGA IP recovers the skew to less than 214UI as per the Interlaken Alliance Interoperability Recommendations. The Interlaken (2nd Generation) Intel® FPGA IP supports significantly more than 258 UI skew tolerance, as can many products in the market.

For L-tile and H-tile variants, soft PCS bonding is implemented, PMA and PCS bonding is not enabled. The TX skew is about 39 UI.

Pin out your Interlaken IP core to exist within a single tile of Intel® Stratix® 10 device. If you have to pin out your core across multiple tiles, please contact Intel Premier Support.

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