Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

1.4. Flexible Lanes Support

In the current version of the Intel® Quartus® Prime Pro Edition software, the IP parameter editor prompts you to the recommended user clock frequency for the combination of number of lanes and data rates. The software derives the user clock frequency based on the configuration you select. The user clock frequency maps to the tx_usr_clk and rx_usr_clk signals.
Table 10.  Recommended User Clock Frequency
Number of Lanes Data/Lane Rate (Gbps) Number of Segments User Clock Frequency (MHz)
H-tile E-tile
4 6.25 1 200 100
12.5 200
25.28 400
25.78 400
25.78125 400
6 25.28 1, 2 300
25.78 300
25.78125 300
8 12.5 1, 2 200
25.28 400
25.78 400
25.78125 400
10 12.5 1, 2 250
25.28 1, 2, 4 250
25.78 1, 2, 4 300
25.78125 1, 2, 4 300
12 10.3125 1 300 250
2 250
12.5 1, 2 300
25.28 1 350
2, 4 300
25.78 1, 2, 4 350
25.78125 1, 2, 4 350
25.5625 (Only in E-tile PAM4 mode IP variations) 1, 2, 4 N/A 350

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