Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Document Table of Contents

2.4. Simulating the IP Core

You can simulate your Interlaken IP variation using any of the vendor-specific IEEE encrypted functional simulation models which are available in the new <instance name>/sim/<simulator> subdirectory of your project directory.

The Interlaken IP supports the following simulators:
  • Siemens* EDA QuestaSim*
  • Synopsys* VCS*
  • Synopsys* VCS* MX
  • Cadence* Xcelium*
The Interlaken IP generates a Verilog HDL and VHDL simulation model and testbench. The IP core parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP core, but the IP core design example does not support a VHDL simulation model or testbench.

For more information about functional simulation models for Intel FPGA IP cores, refer to the Simulating Intel FPGA Designs chapter in Intel Quartus Prime Pro Edition User Guide: Third-party Simulation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message