1.2. Device Family Support
The following lists the device support level definitions for Intel FPGA IPs:
- Advance support — The IP is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support — The IP is verified with preliminary timing models for this device family. The IP meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
- Final support — The IP is verified with final timing models for this device family. The IP meets all functional and timing requirements for the device family and can be used in production designs.
|Intel® Stratix® 10||Final|
|Intel® Agilex™ (with E-tile)||Final|
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