Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

1.5. Round-trip Latency

The following table includes the round-trip latency numbers for specific variants. The latency numbers were measured for the longest logical datapath for two highest lane rate and number of lanes variants, with FIFO level at 50 for the first packet.
Table 11.  Round-trip Latency Numbers
Device Number of Lanes Lane Rate (Gbps) Interlaken Interlaken Look-aside
Number of Segments Latency (Number of tx_usr_clk cycles) Number of Segments Latency (Number of tx_usr_clk cycles)
E-tile (NRZ) 12 25.78125 4 264 1 104
E-tile (PAM4) 6 53.125 4 375 1 219

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