Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.3. High Level Data Path Flow for Interlaken Mode

The Interlaken IP core consists of two paths:
  • Interlaken TX path
  • Interlaken RX path
Each path includes MAC, PCS, and PMA blocks. The PCS blocks are implemented in hard IP.
Figure 7. Interlaken IP Core Block Diagram for L- , H- and E-Tile NRZ Mode Device VariationsThe figure illustrates the 8-word data transfer scenario. This figure uses the following conventions:
  • n = Number of calendar pages
  • m = Number of lanes
Figure 8. Interlaken IP Core Block Diagram for E-Tile PAM4 Mode Device VariationsThe figure illustrates the 16-word data transfer scenario. This figure uses the following conventions:
  • n = Number of calendar pages
  • m = Number of lanes

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