Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 4/04/2022
Public
Document Table of Contents

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 22.1
IP Version 20.0.3

Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The Interlaken (2nd Generation) Intel® FPGA IP implements the Interlaken Protocol Specification, v1.2. This IP also implements Interlaken Look-aside protocol compliant to Interlaken Look-Aside Protocol Definition, v1.1. Interlaken supports multiple combinations of number of lanes (4 to 12) and lane rates from 6.25 gigabits per second (Gbps) to 53.125 Gbps, on Intel® Stratix® 10 and Intel® Agilex™ devices, providing raw bandwidth up to 300 Gbps.

Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken IP incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.

Interlaken Look-aside is a scalable protocol that allows interoperability between a datapath device and a Look-aside co-processor with packet transfer rates up to 300 Gbps.

Figure 1. Typical Interlaken Application

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