Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022

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4.7. IP Core Reset

The Interlaken IP core variations have a single asynchronous reset, the reset_n signal. The Interlaken IP core manages the initialization sequence internally. After you de-assert reset_n (raise it after asserting it low), the IP core automatically goes through the entire reset sequence.

Note: Intel recommends that you hold the reset_n signal low for at least the duration of eight mm_clk cycles, to ensure the reset sequence proceeds correctly.

Following completion of the reset sequence internally, the Interlaken IP core begins link initialization. If your IP core and its Interlaken link partner initialize the link successfully, you can observe the assertion of the lane and link status signals according to the Interlaken specification. For example, you can monitor the tx_lanes_aligned, sync_locked, word_locked, and rx_lanes_aligned output status signals.

The required wait time from de-asserting the reset_n signal to safely accessing the IP core registers is a function of the internal reset controller.

For details on transceiver initialization, please refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide or the E-Tile Transceiver PHY User Guide.