The Interlaken IP supports the following interfaces:
User Data Transfer Interface
The user data transfer interface, also known as application interface, provides up to 256 logical channels of communication to and from the Interlaken link. This interface is similar to the Avalon® Streaming ( Avalon® -ST) interface which supports data bursts or packets, which are carried in the Interlaken meta frame payload.
The Interlaken interface complies with the Interlaken Protocol Specification, Revision 1.2. It is the high-speed transceiver interface to an Interlaken link.
Interlaken Look-aside Interface
The Interlaken Look-aside interface complies with the Interlaken Look-Aside Protocol Specification, Revision 1.1. It is the high-speed transceiver interface to an Interlaken link.
The management interface provides access to the Interlaken IP internal status and control registers. This interface does not provide access to the hard PCS registers on the device. This interface complies with the Avalon® Memory-Mapped ( Avalon® -MM) specification defined in the Avalon Interface Specifications.
Transceiver Control Interfaces
- External PLL Interface
The Interlaken IP variations that target an Intel® Stratix® 10 L-tile or H-tile device require an external transceiver PLL to function correctly in hardware. The Interlaken IP variations that target an Intel® Stratix® 10 or Intel® Agilex™ E-tile device include transceiver PLLs and do not require an external PLL. The E-tile PAM4 mode variations require an additional mac_clkin input clock generated by a PLL. This PLL must use the same reference clock source that drives the pll_ref_clk.
- Transceiver Reconfiguration Interface
The transceiver reconfiguration interface provides access to the registers in the embedded Native PHY IP. This interface provides direct access to the hard PCS registers on the device. This interface complies with the
-MM specification defined in the Avalon Interface Specifications.
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