Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

1.1. Features

The Interlaken (2nd Generation) Intel FPGA IP has the following features:
  • General features:
    • Compliant with the Interlaken Protocol Specification, Revision 1.2.
    • Supports 4, 6, 8, 10, and 12 serial lanes in configurations that provide up to 318.75 Gbps raw bandwidth.
    • Supports per-lane data rates of 6.25, 10.3125, 12.5, 25.28, 25.78, 25.78125, and 53.125 Gbps using Intel FPGA on-chip high-speed transceivers.
  • User interface features:
    • Supports dynamically configurable BurstMax and BurstMin values.
    • Supports Packet mode and Interleaved mode for user data transfer.
    • Supports up to 256 logical channels in out-of-the-box configuration.
    • Supports multi-segment user interface.
  • Flow-control features:
    • Supports optional out-of-band flow control blocks.
    • Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
    • Supports error correction code (ECC) for memory block implementation with the IP.
  • Line-side features:
    • Supports per-lane data rate of 53.125 Gbps using pulse amplitude modulation (PAM4) mode in E-tile variations.
    • Supports per lane data rates of 6.25, 10.3125, 12.5, 25.28, 25.78, and 25.78125 Gbps using non-return-to-zero (NRZ) mode in E-tile variations.
  • PHY features:
    • Supports PMA adaptation.
  • Interlaken Look-aside mode:
    • Supports per lane data rates of 6.25, 10.3125, 12.5, 25.28, 25.78 and 25.78125 Gbps using NRZ and 53.125 Gbps using PAM4 mode in E-tile variations.
    • Supports packet mode for user data transfer.
    • Available only in Intel® Stratix® 10 and Intel® Agilex™ E-tile device variations in current version of the Intel® Quartus® Prime software release.
      Note: Contact Intel Support to request Interlaken Look-aside mode access in IP variations that target an Intel® Stratix® 10 H- and L-tile device.
Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the current version of the Intel® Quartus® Prime Pro Edition software.

Throughout this table, ILK refers to Interlaken mode and ILA refers to Interlaken Look-aside mode.

Device Supported Mode IP Supported Combinations
Number of Lanes Lane Rate (Gbps)1
L-tile ILK only 4 6.25
12.5
25.28
25.78
25.78125
8 12.5
12 10.3125
12.5
H-tile ILK only 4 6.25
12.5
25.28
25.78
25.78125
6 25.28
25.78
25.78125
8 12.5
25.28
25.78
25.78125
10 12.5
25.28
25.78
25.78125
12 10.3125
12.5
25.28
25.78
25.78125
E-tile (NRZ) ILK and ILA 4 6.25
12.5
25.28
25.78
25.78125
6 25.28
25.78
25.78125
8 12.5
25.28
25.78
25.78125
10 12.5
25.28
25.78
25.78125
12 10.3125
12.5
25.28
25.78
25.78125
E-tile (PAM4) ILK and ILA 12 26.56252
Table 2.  IP Theoretical Raw Aggregate BandwidthThe following combinations are supported in the current version of the Intel® Quartus® Prime Pro Edition software:
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5 25.28 25.78 25.78125 26.5625
4 25 - 50 101.12 103.12 103.125 -
6 - - - 151.68 154.68 154.6875 -
8 - - 100 202.24 206.24 206.25 -
10 - - 125 252.8 257.8 257.8125 -
12 - 123.75 150 303.36 309.36 309.375 318.75
Related Information
1 You can customize the data rates depending on the tiles. Refer to the KDB for information on how to customize the data rate.
2 To obtain 6x53.125 Gbps speed in PAM4 mode, select 12x26.5625 Gbps.
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