Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: How-To

Area: Intellectual Property


Last Modified: May 08, 2020
Version Found: v20.1
Bug ID: 14011132198
IP: Interlaken IP Core (2nd Generation)

How do I change the data rate and transceiver reference clock frequency for an Interlaken (2nd Generation) Intel® FPGA IP instance targetting the Intel® Stratix® 10 H-Tile or E-Tile to a value slightly different than what is selected in the IP Parameter Editor GUI?

Description

The Interlaken (2nd Generation) Intel® FPGA IP targetting the Intel® Stratix® 10 H-Tile or E-Tile only supports a select number of data rate and reference clock options in the IP Parameter Editor GUI.

Workaround/Fix

In order to work around this issue, you should perform the following steps to vary the data rate and transceiver reference clock frequency to slightly different values once the the Interlaken (2nd Generation) Intel® FPGA IP instance targetting the Intel® Stratix® 10 H-Tile or E-Tile has been generated.

 

Steps to change the data rate/reference clock frequency when targeting Intel Stratix 10 E-Tile:

  • Change the following line in <IP instance name>/ altera_uflex_ilk_1921/synth/uflex_ilk_core_test_altera_uflex_ilk_1921_<random_suffix>.sdc 

 [Line 31] create_clock -name pll_ref_clk -period "<desired reference clock frequency> MHz " [get_ports pll_ref_clk]

  • Change the following settings in <IP instance name>/altera_xcvr_native_s10_etile_2101/synth/<IP instance name>_ip_parameters_<random_suffix>.tcl

[Line 12] dict set native_phy_ip_params pma_tx_data_rate_profile0 "<desired data rate in Mbps>"

[Line 13] dict set native_phy_ip_params pma_rx_data_rate_profile0 "<desired data rate in Mbps>"

[Line 28] dict set native_phy_ip_params pma_tx_pll_refclk_freq_mhz_profile0 "<desired reference clock frequency in Mhz>"

[Line 30] dict set native_phy_ip_params pma_rx_pll_refclk_freq_mhz_profile0 "<desired reference clock frequency in Mhz>"

 

Steps to change the data rate/reference clock frequency when targeting Intel Stratix 10 H-Tile:

  • Change the following line in <IP instance name>/altera_uflex_ilk_1921/synth/uflex_ilk_core_test_altera_uflex_ilk_1921_<random_suffix>.sdc

 [Line 31] create_clock -name pll_ref_clk -period "<desired reference clock frequency> MHz " [get_ports pll_ref_clk]

  • Change the following setting in <IP instance name>/altera_xcvr_native_s10_htile_1921/synth/<IP instance name>_ip_parameters_<random_suffix>.tcl

[Line 13] dict set native_phy_ip_params set_data_rate_profile0 "<desired data rate in Mbps>"