Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

2.6.2. Adding the External PLL

The Interlaken (2nd Generation) IP core variations that target an L-Tile or H-Tile device require an external TX transceiver PLL to drive the TX transceiver clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.
You can create an external transceiver PLL from the IP Catalog:
  • Select the L-Tile/H-Tile Transceiver ATX PLL Intel® Stratix® 10 FPGA IP.
  • In the parameter editor, set the following parameter values:
    • Set PLL output frequency to one half the per-lane data rate of the IP core variation.
    • Set PLL auto mode reference clock frequency (integer) to the value you select for the transceiver reference clock frequency (pll_ref_clk) parameter in the Interlaken (2nd Generation) IP parameter editor.
    • Set VCCR_GXB and VCCT_GXB Supply Voltage for the transceiver to the same value you specify in the Interlaken (2nd Generation) IP parameter editor.

You must connect tx_serial_clock output from the ATX PLL to tx_serial_clk input of your Interlaken (2nd Generation) IP core.

For more information about ATX PLL connection and how to instantiate the ATX PLL, refer to the Instantiating the ATX PLL IP Core in the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.

To use fPLL as an external transceiver PLL, select L-Tile/H-Tile fPLL Intel® Stratix® 10 FPGA IP from the IP Catalog and set the parameters using the instructions in the Instantiating the fPLL IP Core in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.

The Interlaken (2nd Generation) IP core variations that target an E-tile device contains transceiver PLLs and do not require an external PLL for the transceivers. These transceiver PLLs require a reference clock (pll_ref_clk). Refer to the E-Tile Transceiver PHY User Guide and Interlaken (2nd Generation) Design Example User Guide for the reference clock connections.

The E-tile PAM4 mode variations require an additional mac_clkin input clock generated by a PLL. This PLL must use the same reference clock source that drives the pll_ref_clk. Refer to Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations in Interlaken (2nd Generation) Intel FPGA IP Design Example User Guide for more information about mac_clkin connections.

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