1. About the LL 100GbE IP Core
|Intel® Quartus® Prime Design Suite 16.1|
The Intel® Low Latency 100-Gbps Ethernet (LL 100GbE) media access controller (MAC) and PHY Intel® FPGA IP functions offer the lowest round-trip latency and smallest size to implement the IEEE 802.3ba High Speed Ethernet Standard with an option to support the IEEE 802.3ap-2007 Backplane Ethernet Standard.
The version of this product that supports Intel® Arria® 10 devices is included in the Intel FPGA IP Library and is available from the Intel® Quartus® Prime IP Catalog.
As illustrated, on the MAC client side you can choose a wide, standard Avalon® streaming interface (Avalon-ST), or a narrower, custom streaming interface. The MAC client side Avalon® streaming interface data bus is 512 bits wide. The MAC client side custom streaming interface data bus is 256 bits wide. The client-side data maps to ten 10.3125 Gbps transceiver PHY links or to four 25.78125 Gbps transceiver PHY links.
The 100GbE (CAUI) interface has 10x10.3125 Gbps links. For Intel® Arria® 10 10 GT devices only, you can configure a 100GbE CAUI-4 option, with 4x25.78125 Gbps links.
The FPGA serial transceivers are compliant with the IEEE 802.3ba standard CAUI and CAUI-4 specifications. The IP core configures the transceivers to implement the relevant specification for your IP core variation. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.
The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of configuration and status registers. You can exclude the statistics registers. If you exclude these registers, you can monitor the statistics counter increment vectors that the IP core provides at the client side interface and maintain your own counters.
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