Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

2.7.6. External TX MAC PLL

If you turn on Use external TX MAC PLL in the LL 100GbE parameter editor, you must connect the clk_txmac_in input port to a clock source, usually a PLL on the device.

The clk_txmac_in signal drives the clk_txmac clock in the IP core TX MAC and PHY. If you turn off this parameter, the clk_txmac_in input clock signal is not available.

The required TX MAC clock frequency is 390.625 MHz. User logic must drive clk_txmac_in from a PLL whose input is the PHY reference clock, clk_ref.

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