Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
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3.2.10. Pause Control and Generation Interface

The pause control interface implements flow control as specified by the IEEE 802.3ba 2010 High Speed Ethernet Standard. If you turn on priority-based flow control, the interface implements the IEEE Standard 802.1Qbb. The pause logic, upon receiving a pause packet, temporarily stops packet transmission, and can pass the pause packets through as normal traffic or drop the pause control frames in the RX direction.

Table 20.  Pause Control and Generation SignalsDescribes the signals that implement pause control. These signals are available only if you turn on flow control in the LL 100GbE parameter editor.

Signal Name

Direction

Description

pause_insert_tx[N-1:0] 6

Input

Level signal which directs the IP core to insert a pause frame for priority traffic class [n] on the Ethernet link. If bit [n] of the TX_PAUSE_EN register has the value of 1, the IP core transmits an XOFF frame when this signal is first asserted. If you enable retransmission, the IP core continues to transmit XOFF frames periodically until the signal is de-asserted. When the signal is deasserted, the IP core inserts an XON frame.

pause_receive_rx[N-1:0] 6

Output

Asserted to indicate an RX pause signal match. The IP core asserts bit [n] of this signal when it receives a pause request with an address match, to signal the TX MAC to throttle its transmissions from priority queue [n] on the Ethernet link.

6 N is the number of priority queues. If the IP core implements Ethernet standard flow control, N is 1.

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