Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
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3.2.4.2. LL 100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)

The LL 100GbE IP core RX datapath employs the Avalon-ST protocol. The Avalon-ST protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:

  • Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
  • The SOP must always be in the MSB, simplifying the interpretation and processing of data you receive on this interface.
  • A valid signal qualifies signals from source to sink.

The RX MAC acts as a source and the client acts as a sink in the receive direction.

Figure 21. RX MAC to Client Interface
Table 18.  Signals of the Avalon-ST RX Client InterfaceAll interface signals are clocked by the clk_rxmac clock.

Name

Direction

Description

l8_rx_data[511:0]

Output

RX data.

l8_rx_empty[5:0]

Output

Indicates the number of empty bytes on l8_rx_data[511:0] when l8_rx_endofpacket is asserted, starting from the least significant byte (LSB).

l8_rx_startofpacket

Output

When asserted, indicates the start of a packet. The packet starts on the MSB.

l8_rx_endofpacket

Output

When asserted, indicates the end of packet.

In the case of an undersized packet, or in the case of a packet that is exactly 64 bytes long, l8_rx_startofpacket and l8_rx_endofpacket are asserted in the same clock cycle.

l8_rx_error[5:0] Output Reports certain types of errors in the Ethernet frame whose contents are currently being transmitted on the client interface. This signal is valid in EOP cycles only. To ensure you can identify the corresponding packet, you must turn on Enable alignment EOP on FCS word in the LL 100GbE parameter editor.

The individual bits report different types of errors:

  • Bit [0]: Malformed packet error. If this bit has the value of 1, the packet is malformed. The IP core identifies a malformed packet when it receives a control character that is not a terminate character, while receiving the packet.
  • Bit [1]: CRC error. If this bit has the value of 1, the IP core detected a CRC error in the frame.

    If you turn on Enable alignment EOP on FCS word , this bit and the l8_rx_fcs_error signal behave identically.

  • Bit [2]: undersized payload. If this bit has the value of 1, the frame size is between nine and 63 bytes, inclusive. The IP core does not recognize an incoming frame of size eight bytes or less as a frame, and those cases are not reported here. The l8_rx_error[1] bit also signals an FCS error.
  • Bit [3]: oversized payload. If this bit has the value of 1, the frame size is greater than the maximum frame size programmed in the MAX_RX_SIZE_CONFIG register at offset 0x506.
  • Bit [4]: payload length error. If this bit has the value of 1, the payload received in the frame did not match the length field value, and the value in the length field is less than 1536 bytes. This bit only reports errors if you set bit [0] of the CFG_PLEN_CHECK register at offset 0x50A to the value of 1.
  • Bit [5]: Reserved.
l8_rx_valid

Output

When asserted, indicates that RX data is valid. Only valid between the l8_rx_startofpacket and l8_rx_endofpacket signals.

l8_rx_fcs_valid

Output

When asserted, indicates that FCS is valid.

l8_rx_fcs_error

Output

When asserted, indicates an FCS error condition. The IP core asserts the l8_rx_fcs_error signal only when it asserts the l8_rx_fcs_valid signal.

Runt frames always force an FCS error condition. However, if a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it as a runt.

l8_rx_status[2:0] Output Indicates the IP core received a control frame on the Ethernet link. This signal identifies the type of control frame the IP core is passing through to the client interface.

This signal is valid in EOP cycles only. To ensure you can identify the corresponding packet, you must turn on Enable alignment EOP on FCS word in the LL 100GbE parameter editor.

The individual bits report different types of received control frames:

  • Bit [0]: Indicates the IP core received a standard flow control frame. If the IP core is in standard flow control mode and the cfg_fwd_ctrl bit of the RX_PAUSE_FWD register has the value of 0, this bit maintains the value of 0.
  • Bit [1]: Indicates the IP core received a priority flow control frame. If the IP core is in priority flow control mode and the cfg_fwd_ctrl bit of the RX_PAUSE_FWD register has the value of 0, this bit maintains the value of 0.
  • Bit [2]: Indicates the IP core received a control frame that is not a flow control frame.
Figure 22. Traffic on the TX and RX Avalon-ST Client Interface for Low Latency 100GbE IP CoreShows typical traffic for the TX and RX Avalon-ST interface of the 100GbE IP core.

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